Verilog Help!!!

Discussion in 'OT Technology' started by dbhakta, Jan 26, 2009.

  1. dbhakta

    dbhakta New Member

    Joined:
    Feb 1, 2007
    Messages:
    122
    Likes Received:
    0
    I am trying to program the digilent basys board to take an input signal and display the duty cycle on the sevensegment display but i am getting a whole lot of errors and i dont know what they mean can somebody help me out?

    ERRORS

    Started : "Generate Programming File".
    ERROR:physDesignRules:368 - The signal <CD_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CE_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CF_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CG_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    WARNING:physDesignRules:367 - The signal <CCLK_IBUF> is incomplete. The signal
    does not drive any load pins in the design.
    ERROR:physDesignRules:368 - The signal <AN0_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <AN1_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <AN2_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    WARNING:physDesignRules:367 - The signal <SIGNAL_IBUF> is incomplete. The signal
    does not drive any load pins in the design.
    ERROR:physDesignRules:368 - The signal <AN3_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CDP_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CA_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CB_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:368 - The signal <CC_OBUF> is incomplete. The signal is
    not driven by any source pin in the design.
    ERROR:physDesignRules:10 - The network <CD_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CE_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CF_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CG_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <AN0_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <AN1_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <AN2_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <AN3_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CDP_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CA_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CB_OBUF> is completely unrouted.
    ERROR:physDesignRules:10 - The network <CC_OBUF> is completely unrouted.
    ERROR:Bitgen:25 - DRC detected 24 errors and 2 warnings. Please see the
    previously displayed individual error or warning messages for more details.
     
  2. dbhakta

    dbhakta New Member

    Joined:
    Feb 1, 2007
    Messages:
    122
    Likes Received:
    0
    module dutycount(input CCLK, SIGNAL, output CA,CB,CC,CD,CE,CF,CG,CDP,AN0,AN1,AN2,AN3);

    //wire Low, High, Total;


    clock M0(CCLK, 2500, clk);
    cnthigh M1(HighCnt, clk, SIGNAL, 1);
    cntlow M2(LowCnt, clk, SIGNAL,1);
    Adder M3(clk, HighCnt, LowCnt, Total);
    //Bin2BCD

    endmodule

    module clock(input CCLK, input [31:0] clkscale, output reg clk);

    reg [31:0] clkq = 0;

    always@(posedge CCLK)
    begin
    clkq = clkq+1;
    if (clkq>=clkscale)
    begin
    clk = ~clk;
    clkq=0;
    end
    end

    endmodule

    module cnthigh(output reg highcnt, input clk, signal, reset);

    always@(clk)
    if(reset)
    begin
    highcnt <= 32'b0;
    end
    else if (signal)
    begin
    highcnt <= highcnt + 1;
    end


    endmodule

    module cntlow(output reg lowcnt, input clk, signal, reset);

    always@(clk)
    if(reset)
    begin
    lowcnt <= 32'b0;
    end
    else if (~signal)
    begin
    lowcnt <= lowcnt + 1;
    end


    endmodule

    module Adder(input clk, input[31:0] HighCnt, input[31:0] LowCnt, output reg [32:0]Total);

    integer i;
    reg [31:0]store;
    reg [31:0]highcopy;
    reg [31:0]lowcopy;
    reg AxorB;
    reg AandB;
    reg sum;
    reg carry;
    reg AxorB_andC;



    always@(posedge clk)
    begin
    carry = 0;
    sum = 0;
    highcopy = HighCnt;

    for(i=0; i<=31; i=i+1)
    begin
    AxorB = highcopy ^ lowcopy;
    AandB = highcopy & lowcopy;
    sum = AxorB ^ carry;
    AxorB_andC = AxorB & carry;
    carry = AandB | AxorB_andC;
    store = sum;
    end
    end
    endmodule

    module Bin2BCD(input clk, input[7:0] bindata, output reg [3:0] tensdig, output reg [3:0] onesdig, output reg dataav);

    reg [7:0]value;
    integer i;

    always@(posedge clk)
    begin
    dataav = 0;
    value = bindata;
    tensdig = 0;

    for (i=1; i<=9; i=i+1)
    begin
    if(value >= 100)
    begin
    tensdig = tensdig + 1;
    value = value - 10;
    end
    end
    onesdig = value;
    dataav = 1;
    end
    endmodule

    module svnseg(input SIGNAL, tensdig, output CA,CB,CC,CD,CE,CF,CG,CDP,AN0,AN1,AN2,AN3);

    reg [7:0]cathdata;
    assign CA = cathdata[0];
    assign CB = cathdata[1];
    assign CC = cathdata[2];
    assign CD = cathdata[3];
    assign CE = cathdata[4];
    assign CF = cathdata[5];
    assign CG = cathdata[6];
    assign CDP = cathdata[7];


    always@(negedge SIGNAL)
    begin
    case(tensdig)
    0: cathdata = 8'b00000011;
    1: cathdata = 8'b10011111;
    2: cathdata = 8'b00100101;
    3: cathdata = 8'b00001101;
    4: cathdata = 8'b10011001;
    5: cathdata = 8'b01001001;
    6: cathdata = 8'b01000001;
    7: cathdata = 8'b00011111;
    8: cathdata = 8'b00000001;
    9: cathdata = 8'b00001001;
    endcase


    endmodule
     

Share This Page